The present invention relates to a frame synchronization circuit suitable to transmitting data sequence which have a frame composition in an environment where a code error, especially a data loss or data insertion in units of cells or packets, is likely to be generated.
Conventionally, in a data transmission system in which information data to be transmitted is transmitted in frame units, a method for adding a unique word such as M sequence to each frame as a frame synchronization code has been widely used on its transmitting side. The position to which the unique word is added is not particularly defined in this method, but in general, the unique word is set to the head of a frame to simplify the composition, as shown in FIG. 1A. The unique word in the received data sequence is detected on the reception side, so that the frame position is identified to detect each frame and the transmitted information data is reproduced from each frame detected.
However, there is a disadvantage that an out of detection can occur. This is where detection of the unique word is prevented where the code error is likely to be generated. As such, there is proposed a technique in which the resistance to the burst code error is improved by positioning unique words scatteredly within a frame.
An example of a frame composition according to this technique is shown in FIGS. 1B and 1C. These figures show arrangements of identical unique words. FIG. 1C displays information data for every block of predetermined length (M+1 bits) and FIG. 1B expands the information data for every one bit. In FIG. 1C, unique words are constituted of the most significant bit (bits Sl to SN) of each block, and the signal shown in FIG. 1B can be obtained by expanding the unique words to serial data from high order bit sequentially.
In the example shown in FIG. 1B, the unique words Sj (j=1 to N) are assigned one bit to each uniform interval (M bits) in a transmission information data sequence. However, the intervals assigned may be nonuniform and also plural bits may be assigned. Incidentally, M and N are natural numbers.
Most of the unique words would survive even if a burst code error is generated in a transmission channel by positioning unique words scatteredly in this way, so that a failure to detect any of the unique words is avoided by permitting variations in of the number of constant bits at the time of detection, allowing detection of the unique words with high probability. Incidentally, If the variation in the number of bits is too large compared with the unique word length, false detection may occur, where part of the information data is detected by mistake as a unique word, so that the size of the allowable variation in bits and the unique word length must be set such that the probability of a false detection can be minimized.
Moreover, if a frame length is variable, to achieve higher frame synchronization property, frame length information can also be used in addition to the unique word as a frame synchronization code, as shown in FIG. 1D. An appearance position of the following frame synchronization code can be known on the reception side by using the frame length information, so that the probability of an out of detection or false detection of the frame synchronization code can be reduced compared to the case in which only the unique word is used.
Next, there are described the composition and operation of a conventional frame synchronization circuit. Incidentally, as a method for adding unique words to a frame, a head arrangement or scattered positioning described above can be considered, and there is no influence in the following explanation even if either is adopted.
A. In the Case of a Fixed Length Frame
FIG. 2 shows a composition of a conventional frame synchronization circuit (Example 1). The frame synchronization circuit shown in FIG. 2 may be utilized in a transmission system of a fixed length frame. As shown in FIG. 2, a received data sequence input from an input terminal 11 is sent to a unique word detector 12. In the unique word detector 12, an input buffer 15 buffers the received data sequence sent from the input terminal 11, cuts out data equivalent to the unique word length at every predetermined timing to supply the data to a comparator 16, and then shifts a cut out position of the data by one bit at every same timing.
The comparator 16 compares the data supplied from the input buffer 15 and the unique word sent from a unique word generator 17, and generates a xe2x80x9c1xe2x80x9d when the data is in accordance with the unique word or xe2x80x9c0xe2x80x9d when there is a variation. The single generated by comparator 16 is sent to a synchronization judgment circuit 13 as a comparison result. In order to prevent the out of detection based on code error occurring when comparison operation is performed in the comparator 16, the disagreement of the number of constant bits may be set so as to provide xe2x80x9cagreementxe2x80x9d.
Next, the operation of the synchronization judgment circuit 13 will be described. FIG. 3 is a state transition chart of the synchronization judgment circuit 13. The synchronization judgment circuit 13 is, at first, in an out of synchronization state S1 in which frame synchronization is not established at all. The synchronization judgment circuit 13 in the out of synchronization state S1 transfers its own state to a backward 1 state S2 as xe2x80x9cdetectionxe2x80x9d, when xe2x80x9c1xe2x80x9d is supplied from the comparator 16, and holds its own state in the out of synchronization state S1 as xe2x80x9cout of detectionxe2x80x9d, when xe2x80x9c0xe2x80x9d is supplied.
The synchronization judgment circuit 13 transferred to the backward 1 state S1 skips the received data sequence by the fixed frame length to wait for the output of the comparator 16. When the comparison result from the comparator 16 is xe2x80x9c1xe2x80x9d, the synchronization judgment circuit 13 transfers its own state to a next backward 2 state S3 as xe2x80x9cdetectionxe2x80x9d, and when it is xe2x80x9c0xe2x80x9d, returns back to the out of synchronization state S1 as xe2x80x9cout of detectionxe2x80x9d. The processing similar to that described above is also performed in states after the backward 2, and the state of the synchronization judgment circuit 13 returns immediately back to the out of synchronization state S1 in the case of out of detection, and advances toward a synchronization establishment state S5 when xe2x80x9cdetectionxe2x80x9d continues for total of N+1 times.
Here, the states from the backward 1 to the backward N are set to reduce occurrence frequency of false synchronization, and generally, such setting is called xe2x80x9cbackward protectionxe2x80x9d. When the backward protection is not set up, if the part which agrees with a unique word accidentally exists somewhere in the part other than a unique word in the received data sequence, a false detection which detects the unique word by mistake may occur, resulting in frequent false synchronization. However, the synchronization judgment circuit 13 illustrated in the present invention is provided with backward protection and also repeats agreement judgment for N+1 times to reduce the occurrence frequency of the false synchronization due to false detection.
Moreover, the synchronization judgment circuit 13, even when in the synchronization establishment state S5, skips the received data sequence only by the fixed frame length to wait for an output from the comparator 16. When xe2x80x9c1xe2x80x9d is supplied from the comparator 16, the synchronization judgment circuit 13 retains its own state in the synchronization establishment state S5 as xe2x80x9cdetectionxe2x80x9d, and when xe2x80x9c0xe2x80x9d is supplied, transfers its own state to a forward 1 state S6 as xe2x80x9cout of detectionxe2x80x9d. The processes in the states from the forward 1 to a forward M are opposite those in the states from the backward 1 to the backward N described above, and in the case of xe2x80x9cdetectionxe2x80x9d, the process returns immediately to the synchronization establishment state S5, and when xe2x80x9cout of detectionxe2x80x9d continues for total of M+1 times, the process returns back to the out of synchronization state S1. Furthermore, the states from the forward 1 to the forward M are provided in order to avoid frequent occurrence of xe2x80x9csynchronous errorxe2x80x9d, and such setting is generally called xe2x80x9cforward protectionxe2x80x9d. When the forward protection is not provided, the synchronization may end immediately upon occurrence of the out of detection due to code error. However, the synchronization judgment circuit 13 illustrated in the example of the present invention is provided with the forward protection and repeats the agreement judgment for M+1 times to reduce the occurrence frequency of the xe2x80x9csynchronous errorxe2x80x9d.
B. In the Case of Variable Length Frame
In a transmission system of variable length frame, when only unique words are used as frame synchronization codes, the synchronization can also be established using a circuit of the similar composition as Example 1 shown in FIG. 2, except the function and operation of the synchronization judgment 13. However, in a data transmission system using the variable length frame, the appearance position of the following frame synchronization code can not be determined in advance on the reception side, so that the synchronization can not be established stably by performing the state transfer shown in FIG. 3, and the unique words have to be detected by shifting a received data sequence by one bit sequentially for all frames. For this reason, the trial frequency of the unique word detection will be increased, resulting in higher occurrence frequency of false detection. Therefore, in the example, the composition and operation of the frame synchronization circuit will be described in which not only the unique word but also the frame length information are used as the frame synchronization code.
FIG. 4 shows a composition of a conventional frame synchronization circuit (Example 2) using the unique word and frame length information as the frame synchronization code. In FIG. 4, the common parts to each part of FIG. 2 are identified by the same reference character and their explanations will be omitted. The differences between Example 2 shown in FIG. 4 and Example 1 shown in FIG. 2 are such that the synchronization judgment circuit 13 is replaced with a synchronization judgment circuit 13a and a frame length information detector 18 is newly provided.
The frame length information detector 18 extracts the frame length information followed by the unique word according to the received data sequence input from the input terminal 11 and a frame synchronization output supplied from the synchronization judgment circuit 13a to the output terminal 14, and supplies output data to the synchronization judgment circuit 13a after decoding is performed. Incidentally, when an error is contained in the frame length information, the synchronization judgment for the received data sequence, as will be described hereinafter, may be affected, so that the error correction and detection process (coding and decoding) is often provided to the frame length information in order to improve the reliability of the frame length information.
The synchronization judgment circuit 13a, presumes a position of the following frame synchronization code using the frame length information supplied from the frame length information detector 18 when detecting the frame synchronization code, and skips over the received data sequence to the presumed position concerned to wait for the output of the comparator 16. The operation except having described above is as similar to that of Example 1, therefore, the synchronization judgment according to the state transfer shown in FIG. 3 can be performed as with the fixed length frame, allowing the establishment of the stable synchronization.
Next, a conventional frame synchronization circuit (Example 3) will be explained in which the synchronization judgment is achieved without following the state transfer shown in FIG. 3. In the data transmission system using the variable length frame shown in FIG. 3, the unique word and frame length information are used as the frame synchronization codes, and the error correction and detection processes are premised to be applied to the frame length information. When the frame length information without error is detected in a position followed by the unique word, it is judged that a correct frame synchronization code has been detected. According to Example 3, the occurrence frequency of false detection can be reduced further than if only the unique word is used as the frame synchronization code, so that the frame synchronization position can be judged with high reliability without adopting the state transfer shown in FIG. 3.
As will be apparent from a manner described above, the conventional frame synchronization circuit for fixed and variable length frames operate effectively in either case for a typical code error, such as a random error and burst error, in a conventional transmission system.
However, a transmission system in which a new code error of a different type than that described above may be generated has appeared in recent years. For example, in an ATM (Asynchronous Transfer Mode) transmission, a data loss (cell loss) in packet units of 48 bytes to 53 bytes may occur, when a traffic is too large as compared with transmission channel capacity. Moreover, on an Internet, there has occurred the data loss with a packet unit longer than that described above. Furthermore, in a so-called multimedia transmission, coded data corresponding to plural display media are multiplexed, so that when a code error occurs in information indicating a multiplexed pattern, separating is performed using a wrong pattern, causing data loss or data insertion in packet units.
When a conventional frame synchronization circuit is applied to a data transmission system in which a code error of this type may occur, there appears a problem that the synchronization property is substantially degraded.
Here, there is shown an example of data loss/insertion in FIGS. 5A to 5D. As shown in FIGS. 5A to 5D, when a data loss (packet loss) occurs in a received data sequence FIG. 5A, the length of the frame in which data loss has occurred is made shorter than an original frame length 5B. And, when data insertion (packet insertion) has occurred in the received data sequence 5C, the length of the frame in which data insertion has occurred is made longer than the original frame length 5D.
When the data loss/insertion is generated while the frame synchronization circuit, (Example 1 and 2) as shown in the state transfer of FIG. 3 is in the synchronization establishment state, false frame synchronization positions are output continuously for the number of the frames which is xe2x80x9c1xe2x80x9d larger than the number of stages (M) of the forward protection, causing the continuous synchronous error. In addition, in order to recover the synchronization, the frame synchronization codes of the number, which adds 1 to the number of stages (N) of the backward protection must be detected continuously. That is, there is a disadvantage that the period of synchronous error is long.
Moreover, in order to reduce the time (number of frames) of the continuous synchronous error described above, a countermeasure of reducing the number of stages of the forward and backward protection can be considered. However, when this countermeasure is tried, a drawback will come out which can not maintain the strength to the typical code error, such as a random error or burst error, in a conventional transmission system. Notable, a counter measure without such a drawback is not presently known.
On the one hand, in the frame synchronization circuit (Example 3) which does not use the state transfer of FIG. 3 in a data transmission system using variable length frames, although the continuous synchronous error described above does not occur, frames which are shorter or longer than those expressed with the frame length information included in the frame synchronization code are received, so that the following frame synchronization position can not be detected correctly. Thus, the synchronization codes can not be detected in frames in which the data loss/insertion has occurred and in frames followed by the frames, resulting in synchronous error of at least two frames.
Furthermore, even when the following frame synchronization code can be detected correctly, only an alarm can be issued to indicate errors in the frame length of frames where the data loss/insertion has occurred, so that data with false length which includes discontinuity in the middle of a frame will be output. Therefore, there is a problem in which a decoder (corresponding to display media) followed by the frame synchronization circuit can not decode data from the frame synchronization circuit correctly. In addition, a decoder applied to a transmission channel where code error may exist is often provided with error protection functions, such as error correction function or bit interleave function, but when discontinuity exists in the middle of data supplied from the frame synchronization circuit or the length of a whole data is wrong, the above-mentioned function does not work at all.
The present invention has been made in an attempt to solve the above-described problems, and therefore, has a first object to provide a frame synchronization circuit which can prevent the occurrence of synchronous error due to data loss/insertion while restraining the false synchronization/out of synchronization according to the typical code error, such as random error and burst error, in a conventional transmission system.
It is a second object to provide a frame synchronization circuit which can reduce the adverse effect an a following circuit by correcting a received data sequence.
To solve the above described problem, in the present invention,
a frame synchronization circuit used on a reception side in a data transmission system adopting a frame composition positioning a frame synchronization code scatteredly in a frame includes a frame.
synchronization code detector detecting a frame synchronization code from a received data sequence to output a frame position and a check result by checking a frame synchronization code detected and a correct frame synchronization code and
a data loss and data insertion period judgment circuit determining whether a data loss or data insertion has occurred in said received data sequence according to said check result.